A semiconductor device, such as DRAM (Dynamic Random Access Memory), includes a memory cell area and a peripheral circuit area disposed along the periphery of the memory cell area. Multiple active regions are arranged into matrix formation in the memory cell area, where the active regions are defined by isolation regions with a relatively small width. Multiple active regions are arranged also in the peripheral circuit area, where the active regions are defined by an isolation region with a relatively large width. The isolation regions in the memory cell area and the isolation region in the peripheral circuit area integrate with each other at the border between the memory cell area and the peripheral circuit area.
The isolation regions are created by forming trenches on a semiconductor substrate and filling the trenches with a dielectric film. Specifically, to form the isolation region with a relatively large width in the peripheral circuit area, a dielectric film formed by HDP (High Density Plasma)-CVD (Chemical Vapor Deposition) with better productivity is usually used. To form the isolation regions with a relatively small width in the memory cell area, however, a flowable thin film formed by flowable CVD, etc., may be used. This is because that the HDP-CVD is so inferior in film-burying performance that narrow trenches of 30 nm or less in width cannot be filled sufficiently with a film by the HDP-CVD. Examples of forming an isolation region using a flowable thin film are disclosed in patent document 1 (Japanese Patent Application Publication No. JPA 2010-166026), patent document 2 (Japanese Patent Application Publication No. JPA 2012-231007), and patent document 3 (Japanese Patent Application Publication No. JPA 2014-138053).
Multiple word lines are formed in the memory cell area. These word lines are formed by, for example, forming word trenches on the semiconductor substrate, covering the inner surface of the word trenches with a gate dielectric film on which a conductive film is deposited, and etching back the conductive film. Hereinafter, word lines formed in such a manner will be referred to as “buried word line”. The word lines are arranged such that, for example, two word lines pass through one active region. Patent document 4 (Japanese Patent Application Publication No. JPA 2012-099793) discloses an example in which a plurality of buried word lines is arranged such that two word lines pass through one active region.